Cirrus Logic CS2000 - Extremely versatile programmable clock chip family
- Click image to enlarge
The new Cirrus CS2000, CS2100, CS2200, and CS2300 families are extremely versatile programmable clock devices, building upon Cirrus Logic’s long history as leading supplier of SPDIF and Sample Rate Conversion products. The new devices provide four basic levels of functionality as follows:
- Low cost frequency synthesis/clock generator using internal LCO – CS2300
- Frequency synthesizer/clock generator - CS2200
- Clock multiplier/Jitter Reduction - CS2100
- Full Featured Combination of CS2100 & CS2200: CS2000
- Frequency synthesizer/clock generator, clock multiplier, and jitter reduction
The CS2xxx family is based on a unique hybrid analog-digital programmable phase locked loop. The architecture is unique in many ways, one of which is the ability to provide both frequency synthesizer/clock generator from a stable clock reference and clock multiplication/jitter reduction from a noisy clock source. Another unique attribute is the ability to generate jitter-free clocks relative to noisy input clocks at frequencies as low as 50 Hz. The members of each family are differentiated by the method of control and/or a hardware mode configuration. The CS2xxx-CP is controlled via an I2C /SPI control port and supports the full functionality of the CS2xxx. The CS2xxx-OTP is controlled in hardware mode via 3 mode pins. This functionality of the 8 selectable modes is user defined and configured via the one-time-programmable feature.
No other solution today supports both clock generation and clock multiplication in a single device, goes as low in input frequency (which can be as low as 50 Hz) or has such a range of possible values.
Features
- High-Performance Analog/Digital Phase Locked Loop
- Clock Multiplier / Jitter Reduction
Generates a low jitter 6 - 75 MHz output clock from a jittery or intermittent 50 Hz to 30 MHz clock source - Clock Generation / Frequency Synthesis
Generates a low jitter clock relative to 8 - 75 MHz reference clock - Highly Accurate PLL multiplication factor (<1 PPM error)
- One-Time-Programmable Configuration for Hardware Mode
- I2C / SPI Control Port
- Configurable Auxiliary Output
- Buffered reference clock
- PLL Lock indication
- Second PLL output
- Buffered version of CLK_IN
- Flexible Sourcing of Reference clock
- External oscillator or clock source
- Supports inexpensive local crystal
- No external analog loop-filter components required
- Packaged in a 10-pin MSOP