SC - Highest Performance 90 nm FPGA Family
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PCI Express is a high performance, general purpose Serial I/O Interconnect defined for a wide variety of future computing and communication platforms.
The basic premise of PCI Express is that the host PCI software remains compatible with an endpoint device without new drivers or operating-system software. Salient PCI attributes, such as its usage model, load-store architecture, and software interfaces, are maintained, whereas its bandwidth-limiting and parallel bus implementation is replaced by a highly scalable, fully serial interface.
PCI Express takes advantage of recent advances in point-to-point interconnects, switch-based technology, and packetized protocol to deliver new levels of performance and features.
LatticeSC Features for PCI Express:
- High Performance FPGA Fabric
- 15K to 115K Four Input Look-up Tables (LUT4s)
- 139 to 942 I/Os
- 700MHz global clock; 1GHz edge clocks
- High Speed SERDES: 4 to 32 SERDES per device @ 600Mbps to 3.8Gbps featuring
- Pre-emphasis and equalization
- Low Power (105mW per Channel)
- Embedded Physical Coding Sublayer (PCS) supports: PCI Express GbE, XAUI, SONET, 1G Fibre Channel, 2G Fibre Channel and Serial Rapid IO
- PURESPEED Technology: 2Gbps Parallel I/O
- Input Delay (INDEL) with Adaptive Input Logic (AIL) dynamically aligns data on a per-pin basis for robust high performance source synchronous I/O support
- Supports generic DDR up to 2Gbps; generic SDR up to 1Gbps; Single-ended memory interfaces up to 800Mbps
- Comprehensive standards support: LVCMOS; LVTTL; PCI, PCI-X; LVDS, Bus-LVDS, MLVDS, LVPECL; with programmable On Device Termination (ODT) options