Lattice's FreedomChip custom tests standard LatticeSC/M FPGAs to your specific design using proven ASIC scan-based test methodologies.

This provides you with a high quality, cost reduced FPGA for high volume applications with prototypes available in mere weeks.

FreedomChip provides you with the benefits of structured ASIC pricing at a fraction of the associated NRE, while avoiding the lengthy technical challenges and risks associated with a design conversion. Moreover, since it uses the same LatticeSC/M FPGA die and package, FreedomChip functionality, performance, signal integrity and power consumption characteristics are identical to the FPGA it replaces.

Unlike other custom-tested FPGA approaches, the FreedomChip methodology incorporates high quality, scan based test methodologies utilizing unique in-built FPGA circuitry to provide the industry's highest fault coverage for FPGAs. Verifiable fault coverage reports are available as part of the FreedomChip process.

Best of all, Lattice ispLEVER design tools do all the work - no special design tools are needed to target FreedomChip devices. FreedomChip design is seamless: target FreedomChip when you start your FPGA design and all test structures are transparently inserted.

Scan test reduces testing complexity by using scan registers throughout the design. The scan chain reduces the need for sequential tests to observe fault sites. Most faults can be tested with a single clock cycle.

This greatly simplifies the test generation problem and allows the use of automated tools to achieve near 100% test coverage.

The standard register structure used in LatticeSC devices is a dual-input register as illustrated in the figure below.

This input can be used as the scan input in the FreedomChip flow without requiring any additional overhead for that register.