LatticeMico32 Architecture

The LatticeMico32 microprocessor uses fewer than 2,000 Look Up Tables (LUTs), which results in a cost of less than $1.00 of FPGA logic in select LatticeECP2™ FPGAs in high volume. The Reduced Instruction Set Computer (RISC), Harvard-based architecture uses 32-bits for data path and instructions and supports optional data and instruction caches, as well as user-defined instructions. 
The LatticeMico32 is distinct from other FPGA embedded microprocessors with exclusive features that include:

• 32 general purpose registers
• Up to 32 external interrupts
• Dual Wishbone memory interface

The LatticeMico32 maintains the high performance required for a breadth of applications, with a maximum clock frequency of over 100 MHz (estimated) for LatticeECP2 FPGAs.

To accelerate the development of microprocessor systems, several optional peripheral components may be integrated with the LatticeMico32. These peripheral components are connected to the microprocessor via a Wishbone bus interface, which is a royalty-free, public domain specification. The peripheral components include:

Memory controllers

• Asynchronous SRAM
• On-Chip block memory

Input/Output (IO) ports

• 32-bit timer
• Direct Memory Access (DMA) controller
• General Purpose IO (GPIO)
• I2C master controller
• Serial Peripheral Interface (SPI)
• Universal Asynchronous Receiver Transmitter (UART)

LatticeMico32 System Development Tool Suite
The LatticeMico32 System development tools, based on the Eclipse C Development Tools (CDT) environment, seamlessly integrate with the Lattice ispLEVER tool suite (version 6.0 SP1 or higher) to enable designers to build microprocessor systems on Lattice FPGAs. The LatticeMico32 System is comprised of three tools: the Mico System Builder (MSB), the C/C++ Software Project Environment (SPE) and the Debugger. The MSB generates platform descriptions and the associated HDL code for hardware implementation. It also enables designers to choose which peripherals should be attached to the microprocessor and the connectivity between them. The C/C++ SPE calls a GNU-based compiler, assembler and linker and enables the development of code targeted to run on platforms created with the MSB. The Debugger allows the designer to observe and control the execution of the code in both an Instruction Set Simulator (ISS) and in physical hardware.

LatticeMico32 Development Kit
To help users rapidly evaluate their microprocessor designs in hardware, Lattice provides a LatticeMico32 Development Kit that includes Lattice's award-winning ispLEVER software design tools, the LatticeMico32 System development tool suite and a development board. The board is packed with features that help the designer get maximum value from the hardware evaluation process, including Flash memory for loading programs, optional LCD and keyboard interfaces and a variety of other peripheral interfaces including Ethernet, USB and RS232. 

Open Source License
The LatticeMico32 is unique among the microprocessors offered by FPGA vendors in that the generated microprocessor and selected peripheral HDL code are licensed under Lattice's open source license agreement. This unique license allows users to ensure that their proprietary designs remain proprietary and allows the implementation and distribution of hardware without the need for a separate license agreement. Additionally, the GNU-based compiler, assembler, linker and debugger, supplied by Lattice, are released under the standard GNU General Public License (GPL) agreement.  This open source approach benefits designers by providing:

Visibility: Allows better understanding of the intrinsic details of the core's architecture and operation.

Flexibility: Allows the user community to identify areas for enhancement, help develop higher quality solutions and make modifications.

Portability: Provides architecture independence, so that a design can be migrated to other hardware platforms such as ASICs or other programmable devices.