The XAUI/HiGig™/HiGig+™ to SPI4.2 (X2S4) bridge for LatticeSCM devices is the industry's lowest power programmable Fabric Interface Chip (FIC) solution. The solution, which utilizes the LatticeSCM's System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability, and includes Lattice's 10Gb+ Ethernet Media Access Controller (MAC) soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design, provides a high-performance interface between the SERDES-based XAUI standard, used ubiquitously in 10Gb Ethernet networks, and SPI4.2, a very popular parallel bus interface used by Network Processor Unit (NPU) devices.
New 10 Gigabit Ethernet Service Cards are being implemented to support additional features and services. These cards are found in Metro Switches, Edge and Core Routers, Ethernet Backbone Switches, Aggregation Routers, Access Nodes, etc. The key functional silicon nodes on these cards are Ethernet Switches and Network Processors.

Shown below is an example of a 10Gb Ethernet Services card implementation using an Ethernet Switch device and a Network Processor. The physical interface to the Ethernet Switch devices is SERDES, supporting protocols like GE, SGMII, 2.5 GE/SGMII, XAUI, HiGiG, HiGig+. HiGig is a Broadcom proprietary interconnect scheme for the StrataXGS family. The HiGig protocol supports various switching functions like Quality-of-Service (QoS), link aggregation, etc. HiGig+ is a higher rate version of HiGig. The 10G NPUs typically have a SPI4.2 interface to link to the fabric. Hence, a Fabric Interface Chip (FIC) is required to bridge from the SPI4.2 on the NPU to the SERDES interface (GE/2.5GE/XAUI/HiGig/HiGig+) interface on the Ethernet Switch.

The LatticeSCM family with its industry-leading SERDES/PCS and built-in MACO (Masked Array for Cost Optimization) blocks implementing high performance, low power SPI4.2 interfaces, is a perfect fit for implementing these bridging solutions.