Web Link
Contact
To request info - click here
To arrange a demonstration - click here
For further information -
mailto: Joerg Siemers
SERDES-Capable LatticeECP3Family Consumes Half the Power and is Half the Price of Competitive Devices
- click image to enlarge
Lattice Semiconductor have announced its third generation high value FPGAs, the mid-range 65nm LatticeECP3™ family, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology, and is the only 65nm mid-range, high value FPGA family in the industry.
The five devices that comprise the low power LatticeECP3 FPGA family all offer standards-compliant multi-protocol 3G SERDES, the industry’s only DDR3 memory interface for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
The LatticeECP3 FPGA family’s high performance features include
- 3.2Gbps SERDES with 10GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and Gigabit Ethernet.
- The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
- Compliance to the SMPTE Serial Digital Interface standard, with the unprecedented ability to support 3G, HD and SD video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
- DSP slices allowing up to 36x36 Multiply and Accumulate blocks in each slice running at 500MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
- 800Mbps DDR3 memory interfaces, with built-in read and write leveling.
- 1Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADC and DACs.
With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications.
The LatticeECP3 FPGA family is supported by the ispLEVER® design tool suite, version 7.2 Service Pack 1, which also has been announced today. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER software is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. The ispLEVER design tool suite includes Synopsys’ Synplify Pro® synthesis for all operating systems supported and Aldec’s Active-HDL™ Lattice Edition simulator for Windows.