LatticeMico32 Open, Free 32-Bit Soft Processor
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The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement. Everything you need is provided, including software development tools and an evaluation board to try out your designs in hardware.
LatticeMico32 Core and Peripheral Overview
The LatticeMico32™ is a highly configurable 32-bit Harvard architecture "soft" microprocessor core for Lattice FPGA devices. By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a RISC architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set.
To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.
Key Features and Benefits
- Optimized for Lattice FPGA Devices
- Performance Enhanced Feature Set
- RISC architecture
- 32-bit data path and 32-bit instructions
- 32 general purpose registers
- Handles up to 32 external interrupts
- Optional instruction and data caches
- Dual WISHBONE memory interfaces (Instruction and Data)
- Port of uC/OS-II RTOS from Micrium
- WISHBONE Compatible Peripheral Components
- Memory controllers
- Asynchronous SRAM
- On-chip block memory
- I/O
- 32-bit timer
- DMA controller
- GPIO
- I2C master controller
- SPI
- UART