
Cortex M1 - The ARM® Processor Designed for FPGAs
Developed by ARM in collaboration with Actel, the 32-bit ARM Cortex™-M1 processor is the first ARM processor designed for FPGA implementation. With a balance between size and speed, the free Cortex-M1 processor operates at up to 68 MHz and can be implemented in as few as 4,410 tiles.
A streamlined three-stage pipeline solution, the Cortex-M1 processor runs a subset of the classic Thumb®-2 instruction set so existing Thumb code can be utilized without change. The configurable Cortex-M1 processor connects to the Advanced High Performance Bus (AHB), enabling designers to build their subsystem and easily add peripheral functionality.
Features
- Developed specifically for FPGA implementation
- ARMv6-M instruction set architecture
- Executes all Thumb code—can run ARM7 and ARM9 Thumb subroutines
- 3-stage, 32-bit pipeline
- Separate memory and AHB-Lite interfaces
- Configurable nested vectored interrupt controller
- Optional fast or small multiplier
- Upward compatible with Cortex-M3
- User-programmed into the FPGA
- All Cortex-M1 I/Os and signals are accessible to the user
- Optimized for Actel flash-based M1 devices
- Available with no license fees or royalties
- Embedded real-time debug and JTAG interface
- Supported by a full range of development tools
Cortex-M1 Actel Devices
Cortex-M1 is available for use in M1 flash family devices, which have been made ARM-enabled for seamless use of the processor core.
M1 Devices | 250 | 600 | 1000 | 1500 | 3000 |
M1 Fusion | x | x |
| x | |
M1 Igloo | x | x |
|
| x |
M1 ProASIC3L | x |
|
| x | |
M1 ProASIC3 | x | x |
| x | x |
Intellectual Property
There is an important set of functional blocks that’s required for Cortex-M1 embedded applications. Actel offer a number of free IP cores to support the Cortex-M1, for example common peripherals such as I2C and SPI.
For a full list of available free IP Cores or more information on how to implement them in your design, please contact your local Avnet-Memec office for technical support.
