Announced on the 26th August its entire ExpressLane™ PCIe Gen 2 switch family, ranging from four to 96 lanes, is fully compliant to support Access Control Service (ACS), which is required in PCIe switches in various I/O virtualization (IOV) applications.  Virtualization allows multiple operating systems running simultaneously within a single computer to share CPU and I/O resources.  ACS capability in PLX® PCIe switches prevents silent data corruption and un-intended data transfers between partitions of shared resources in virtual computing environments found in modern data centers.  Virtual computing is increasingly being deployed in data centers to reduce capital expenditures and operating expenses.

All PLX Gen 2 switches also support Alternative Routing-ID Interpretation (ARI), which increases the number of functions a device may support.  Additionally, PLX PCIe Gen 2 switches support Multicast (MC), which allows a single ingress packet to be sent to multiple egress ports, delivering significant saving in CPU utilization.

ACS, ARI and MC were announced as engineering change notices (ECNs) by the PCI-SIG® and later included in PCI Express Base Specification 2.1.  ACS defines a set of control points within a PCIe topology to determine whether a packet should be routed normally, blocked or redirected.  ACS is applicable to root complexes (RCs), switches and multi-function I/O devices. 

In PCIe packets, routing IDs, requester IDs, and completer IDs are 16-bit identifiers traditionally composed of three fields: an 8-bit bus number, a 5-bit device number, and a 3-bit function number.  With ARI, the 16-bit field is interpreted as two fields instead of three: an 8-bit bus number and an 8-bit function number; the device number field is eliminated.  This new interpretation allows an ARI-enabled device to support up to 256 functions instead of eight, which allows higher device integration and provides better utilization of server CPU for virtual machines or system images.

Multicast defines the process for copying a single packet on an ingress port to multiple egress ports of a PCIe switch.  Multiple groups of ingress/egress ports can be configured for MC, thus providing additional flexibility in moving traffic or storing information.  PLX pioneered this idea in PCIe and helped define it for the PCI-SIG specification.

ACS, ARI and MC are detailed in the PCI-SIG’s PCI Express Base Specification 2.1 which can be found on the PCI-SIG Website.