Silicon Labs, together with Avnet Memec EMEA, has leveraged its proven DSPLL® technology to create the industry's first family of clock ICs that support any-rate frequency synthesis, jitter attenuation, and clock distribution at jitter levels of 0.3 picoseconds.

This phase-locked loop (PLL) technology uses digital signal processing (DSP) techniques to move traditionally analog PLL functions into the digital domain. The devices integrate a high-performance, low phase noise VCO, loop filter, phase detector, dividers, input clock selection mux, and flexible output buffers on-chip.

This eliminates the need for expensive VCXO / VCSOs, discrete loop filters, muxes, clock buffers, and level translators.

Targeting high-performance timing applications, this revolutionary architecture provides outstanding frequency flexibility and jitter performance.

The any-rate precision clocks provide an upgrade path for Si5320/21/64 customers and complement Silicon Labs' existing XO/VCXO products by providing the industry's most comprehensive portfolio of frequency flexible, low jitter timing solutions.

Silicon Labs any-rate precision clocks address the growing need for frequency-flexible, low jitter clock sources in next generation networking equipment, telecom infrastructure, wireless base stations, broadcast video, test and measurement, and data acquisition.

These products greatly simplify high-speed clock designs, facilitate design reuse, lower system costs, shorten lead times, and improve performance in these applications.

Silicon Labs any-rate precision clocks provide clock multiplication, jitter attenuation, and clock distribution in high-performance timing applications.

The devices accept multiple clock inputs ranging from 2 kHz to 710 MHz and generate up to five low-jitter, independent, synchronous differential clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz.

The μP-controlled devices listed below provide virtually any frequency translation combination across this operating range. For ease of use, pin-controlled devices are available that are preconfigured to support 275 popular SONET, Ethernet, Fibre Channel, and broadcast video (HDTV) frequency plans.

Silicon Labs offers the industry's most comprehensive portfolio of low jitter clocks. Some provide any-rate frequency synthesis and jitter attenuation for the most demanding, jitter-sensitive applications. Others are low jitter clock multipliers targeting more cost-sensitive applications where jitter requirements are not as stringent. Devices are offered in two package options: a 6x6 mm 36-lead QFN for devices with 1 or 2 clock outputs and a 14x14 mm 100-lead TQFP for products with 5 clock outputs. All products are Pb-free and RoHS6 compliant.

Silicon Labs also offer a PC-based software utility, DSPLLsim, that can be used for device selection, frequency planning, loop bandwidth selection, and general device configuration. DSPLLsim is a key design tool to demonstrate the ease of use and frequency flexibility of the any-rate precision clocks. This utility is available to download from http://www.mysilabs.com/SalesGuide/Timing/PrecisionClockICs

Silicon Labs any-rate precision clocks utilise proprietary DSPLL technology to generate the low jitter clocks required in precision timing applications. The DSPLL approach takes advantage of digital signal processing (DSP) algorithms to create a highly integrated PLL. In this DSP-based PLL architecture, the phase detector output is converted to digital format by a high speed analog-to-digital converter (ADC). Following the ADC, all signal processing is done in the digital domain using high-speed DSP algorithms. Because the loop filter is implemented digitally, the PLL bandwidth is configurable, providing a range of input clock jitter filtering options - a Silicon Labs exclusive feature. The heart of the DSPLL is a low phase noise, high-frequency on-chip digitally controlled oscillator (DVCO) that rivals the jitter performance of the best VCXOs or VCSOs while providing a tuning range that is over three orders of magnitude greater than VCXOs or VCSOs. As a result, one any-rate precision clock can support a wide range of input/output clock frequencies that would normally require multiple VCXO or VCSO-based PLLs. An optional crystal or reference clock is required to support jitter attenuation some devices, but is not required on the low jitter clock multipliers.

• Any-rate frequency synthesis
• Internal loop filter
• Hitless switching  
• Multiple, frequency flexible input and output clocks
• Selectable output clock format (LVPECL,LVDS, CML, CMOS)
• Comprehensive alarm monitoring (LOL,LOS, FOS)
• Digital hold  
• Low jitter (0.3 ps RMS 12kHz-20MHz, 0.3ps RMS 50kHz-80MHz)
• CMOS-based DSPLL IC