Next-generation timing architectures require a wide range of frequencies that are often non-integer related.  Traditional clock architectures address this by using multiple single PLL ICs, often at the expense of BOM complexity and power.  The Si5334 and Si5338 use patented MultiSynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions.  Based on a fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO.  The VCO supplies a high frequency output clock to the MultiSynth block on each of the four independent output paths.  Each MultiSynth operates as a high-speed fractional divider with Silicon Laboratories’ proprietary phase error correction to divide down the VCO clock to the required output frequency with very low jitter. 

The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error.  To eliminate phase error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance.  Based on this architecture, each output clock can be individually programmed to generate any frequency from 0.16 to 350 MHz and select frequencies to 700 MHz.

Si5330/34/38 Any-Rate, Any-Output Clock Generators and Clock Buffers

The Si5338 Any-Rate, Any-Output Quad Clock Generator is an I2C programmable clock capable of synthesizing any frequency on each of the device’s four differential outputs with outstanding jitter performance. The device architecture is based on Silicon Labs’ breakthrough MultiSynth technology, which dramatically simplifies timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (PLLs) in a single device.  To provide additional design flexibility, each output clock is independently user-programmable to support any signal format and reference voltage.  This dramatically simplifies timing architectures by replacing fixed frequency clock generators, discrete level translators and crystal oscillators (XOs) with a single device while minimizing cost, real estate and power.

For applications where an I2C interface is not available or not desirable, Silicon Labs is introducing the Si5334 Pin-Controlled, Any-Rate, Any-Output Quad Clock Generator.  Approximately 70 Si5334 clock generators are available that support popular frequency translations for a broad range of applications.  To further simplify timing architectures, Silicon Labs is introducing the Si5330 Low Jitter, Low Skew Clock Buffer.  The Si5330 targets clock distribution applications and supports a broad range of clock format options.  This product portfolio supplements Silicon Labs’ existing XO/VCXOs, any-rate jitter attenuating clock multipliers, and silicon oscillators, providing the industry’s broadest portfolio of timing products and enabling Silicon Labs to offer customers a complete clock tree solution in next generation designs.