Silicon Labs addresses high-volume, low-cost reference clock applications with an innovative all-silicon oscillator product family. This is the industry’s first completely silicon oscillator that is truly capable of replacing quartz-based oscillators.  The Si500 family offers shorter lead times, lower costs, higher reliability, and higher performance than existing oscillators.  The Si500 supports the widest frequency range (0.9 to 200 MHz), widest selection of signal formats and lowest jitter (0.9 ps RMS period jitter) of any commodity oscillator on the market today with total power consumption that is among the best in the industry.  The Si500 is drop-in compatible with existing 3.2x5 mm XO designs.

Quartz-based oscillators have been plagued with unpredictable delivery times and supply availability due to their manufacturing complexity.  The all-silicon Si500 oscillator eliminates the need for quartz resonators and dramatically simplifies the XO supply chain by leveraging standard, high volume IC manufacturing technology, enabling 2 weeks lead times for samples and 4-6 weeks for production orders of any frequency oscillator.  Based on this innovative supply chain, the Si500 provides a cost-effective solution when compared to traditional oscillators.

The Si500 provides a much more reliable solution than quartz-based oscillators, providing a Failure In Time (FIT) rate that is more than 10x lower than competing solutions.  Quartz oscillators use a mechanical resonator that vibrates at the desired frequency, making the device susceptible to shock and vibration.  Since the Si500 has no moving parts, it is not susceptible to shock and vibration effects.  In addition, the Si500 provides superior reliability at start up and during long-term operation.

The Si500 is the first silicon oscillator in the industry to support differential clock outputs (LVPECL, LVDS, HCSL) in addition to CMOS and SSTL formats, providing customers added design flexibility.  The Si500 is the industry’s only oscillator to support a dual output CMOS format mode in which a single device can produce two output clocks at the same frequency, eliminating the need for external clock buffers.