Silicon Labs now offers clock tree design and consulting services to help you simplify design and layout. You now have quick access to Silicon Labs’ experienced applications engineering team, willing to provide custom timing architecture proposals that simplify design, reduce BOM costs and minimize risk during development.  When combined with the industry’s shortest component lead times of two weeks or less, Silicon Labs’ clock and oscillator family is designed to accelerate your time to market.

Performance-sensitive applications often require a combination of oscillators, clock generators and clock buffers to provide critical reference timing to high-speed SerDes devices, FPGAs, processors, data converters (ADC/DACs) and digital signal processors (DSPs). Not only is individual timing component selection critical, but system-level requirements also need to be taken into account to optimize performance.

With the Silicon Labs’ online Clock Tree Design Service, you can enter system-level timing requirements using a web-based utility.  Just specify multiple parameters—the number of clock inputs and outputs, input and output frequencies, signal formats and clock jitter. Our applications engineering team will then review the requirements and provide a timing architecture optimized for performance, cost and lead time. We will also provide layout reviews and schematic reviews of all designs created using this program. Timing proposals are provided back to you in just three business days!