The Si5317 Jitter Cleaning Clock is the industry’s most frequency flexible solution for applications that require jitter attenuation without clock multiplication.  Clock cleaners provide jitter filtering, removing unwanted noise sources and producing a low jitter output.  The Si5317 leverages patented DSPLL® technology with industry-best tenability and removes noise on any clock signal ranging from 1 to 710 MHz.  It also produces two ultra-low jitter output clocks at the same frequency.  All PLL circuitry is integrated on-chip and all device configurations are made via pin settings.  This minimizes design time and layout complexity while eliminating the need for firmware and serial programming.  The Si5317 provides a simple, convenient, cost-effective jitter filtering solution for performance-sensitive applications.

By definition, clock jitter is the deviation of a clock edge from its ideal position. Managing clock jitter is very important in high-speed applications since jitter degrades overall system performance.  Jitter impacts the bit-error-rate (BER) and signal-to-noise Ratio (SNR) in the design. Understanding clock jitter helps you better understand system timing margin for an overall clock tree.  As hardware designs migrate to higher speeds and greater complexity, the design of timing architectures has become a critical component in the overall system design.

The Si5317 jitter cleaning clock accepts a dirty (jittered) reference clock, attenuates this jitter using its internal DSPLL, and generates two clean output clocks with very low jitter (300 fs rms).  All PLL components are integrated in a single IC, providing outstanding frequency tunability, excellent jitter performance and ease of use.  This simplifies timing architectures while minimizing cost and board space requirements.  Silicon Labs’ DSPLL® technology integrates all key components of a high-performance analog PLL on chip including a low phase noise voltage-controlled oscillator (VCO), loop filter components, phase detector, divider and buffers—all while providing outstanding jitter performance.
If you are a customer designing data communication and telecom access equipment, you may require jitter-filtered clocks for FPGA-based high-speed serial links and optical 10 G SerDes/PHYs. Some key applications that would enjoy the benefits of the Si5317 include wireless backhaul, DSLAMs, multi-service access nodes (MSAN), GPON/EPON OLT line cards, and 10 G switches and routers.

The Si5317 easily connects to other timing products from Silicon Labs, including the Si5xx XO/VCXOs, the Si5338/34 <710 MHz any-rate differential clock generators, the Si5355/56 <200 MHz any-rate CMOS clock generators, and Si5330 low jitter clock buffers.   Silicon Labs offers a wide portfolio of jitter attenuating clocks, low jitter clock multipliers, frequency flexible clock generators, and buffers.  The Si5317 and the Si5316 are jitter cleaners and do not provide clock multiplication.   Whereas the Si5316 is optimized for 10 G module applications, the Si5317 can be used in any jitter-sensitive application given its expanded frequency range.  The Si5317 is pin-compatible with other pin-controlled devices including the Si5315/16/22/23.