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 Product Datasheet (English, 104 KB)

 Reference Design Schematics (English, 44.9 KB)

 BOM (English, 21.9 KB)

 

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LAN9218I - High-Performance 10/100 Ethernet Controller with HP Auto-MDIX

The LAN9218I is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required.

 

The LAN9218I has been specifically architected to provide the highest performance possible for any given architecture.

 

The LAN9218I is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.


Following in the vein of SMSC's other successful 10/100 Base T Ethernet controllers, the LAN9218I is an advanced architecture single chip solution integrating MAC, PHY, a pseudo-SRAM slave interface, large capacity / high bandwidth TX/RX FIFO?s and efficient memory buffers. 
Of particular note for designers are those features designed to remove or significantly decrease data packet drop-out, as well as several power management modes, harmonised with remote or external Ethernet wake-up signals for triggering system power-up from sleep states.


The LAN9218I is targeted primarily for those high-end consumer multimedia applications such as premium set-top box, hotel video on demand distribution systems, HDTV and digital video recorders, as well as communication infrastructure like home gateways, VOIP, WLAN and digital media clients / servers.
The low profile Pb-free 100-pin TQF package is easily migrated from existing LAN9118 family devices, requiring only a negligible board-level alteration, and is available with either matte tin or tin-copper finish.  
The LAN9218I is fully supported with extensive resources such as references design schematics and bill of materials detailing the specification of 25MHz Crystal, MAC EEPROM and decoupling capacitors, and a plethora of source code drivers including Linux, WinCE 5.0, and X-Scale "eBoot".

Features

  • Single chip Ethernet controller 
  • Fully compliant with IEEE 802.3/802.3u standards
  • Integrated Ethernet MAC and PHY
  • 10BASE-T and 100BASE-TX support
  • Full-duplex flow control
  • Half-duplex flow control with Backpressure
  • Preamble generation and removal
  • Automatic 32-bit CRC generation and checking
  • Automatic payload padding and pad removal
  • Loop-back modes  
  • Various Flexible address filtering modes 
  • Integrated 10/100 Ethernet PHY supports HP Auto-MDIX
  • Supports energy-detect power down & Auto-negotiation
  • High-Performance host bus interface  Simple, SRAM-like interface
  • 32/16-bit data bus
  • 16Kbyte FIFO with flexible TX/RX allocation
  • One configurable host interrupt 
  • Low profile lead-free 100-pin TQFP package
  • Integrated 1.8V regulator; General Purpose Timer; Optional EEPROM interface
  • Support for 3 status LED's multiplexed with Programmable GPIO signals 
  • 3.3V Power Supply with 5V tolerant I/O; -40° to +85°C