Timing Solutions offerings fall into the following categories:

• PLL, DPLL, DSPLL, APLL
• XO, VCXO, TCXO
• Single Crystal Input, VCO, Multi-Synthesiser

PLL, DPLL, DSPLL, APLL

PLLs generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.

• PLL – Phase Lock Loop
• DPLL – Digital Phase Lock Loop uses some (not all) digital components eg phase detector or digital divider but the VCO will remain Analogue
• APLL – Analogue Phase Lock Loop have analogue or Linear o/ps
• DSPLL – Digital Signal Processor Phase Lock Loop – Silicon Labs Clock/DSPLL technology provides any frequency synthesis and 300fs rms jitter performance in a highly integrated PLL solution eliminating the need for external VCXO and loop filter components.

XO/VCXO/TCXO

Crystal oscillator circuits are often designed around relatively few standard frequencies, such as 3.579545 MHz, 10 MHz, 14.318 MHz, 20 MHz, 33.33 MHz, and 40 MHz.

• XO – Crystal Oscillator
• VCXO – Voltage Controlled Crystal Oscillator, the frequency of oscillation is varied by the applied DC voltage. Silicon labs offer factory user specifications eliminating long lead-times associated with customer oscillators
• TCXO – Temperature Controlled Crystal Oscillator to stabilise frequency variation over temperature.

Single Crystal Input, VCO, Multi-Synthesiser

Multi Synthesisers can generate multiple clocks from a single crystal, allowing designers to replace numerous oscillators traditionally used to provide timing for various components with one chip. The free run synchronization solution reduces the need for multiple costly components with a highly integrated and programmable, single-chip solution. This combination of technologies enables any frequency to be generated on any output. The Crystal or reference clock input is synthesised internally in some cases using and internal VCO (Voltage controlled oscillator). Thus eliminating the need for multiple chips and also MOQs associated with ordering custom clock generators.

Click on the Link to Avnet Memec’s Timing and Clock Solutions Brochure to find out more about our supplier offerings: